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? semiconductor components industries, llc, 2010 may, 2010 ? rev. 0 1 publication order number: ncp3127/d ncp3127 2 a synchronous pwm switching converter the ncp3127 is a flexible synchronous pwm switching buck regulator. the ncp3127 is capable of producing output voltages as low as 0.8 v. the ncp3127 also incorporates voltage mode control. switching frequency is internally set. the ncp3127 is currently available in an soic ? 8 package. features ? 4.5 v to 13.2 v operating input voltage range ? 80 m high ? side and low ? side switch ? output voltage adjustable to 0.8 v ? 2 a continuous output current ? fixed 350 khz pwm operation ? 1.0% initial output accuracy ? 75% max duty ratio ? short ? circuit protection ? programmable current limit ? this is a pb ? free device typical application ? set top boxes ? dvd drives and hdd ? lcd monitors and tvs ? cable modems ? telecom / networking / datacom equipment figure 1. typical application circuit ncp3127 fb1 3.3 v bst vsw pgnd agnd iset comp vin 4.5 v ? 13.2 v 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 figure 2. efficiency (v in = 12 v) vs. load current efficiency (%) output current (a) 5 v soic ? 8 nb al suffix case 751 marking diagram http://onsemi.com pin connections 1 8 3127 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 3127 alyw 1 8 vsw iset vin bst pgnd fb comp agnd ncp3127 1 (top view) see detailed ordering and shipping information in the package dimensions section on p age 23 of this data sheet. ordering information
ncp3127 http://onsemi.com 2 circuit description uvlo por clock ramp osc pwm comp ? scp fb vin vsw pgnd + + ? osc comp agnd vref latch fault + ? r pwm out s q fault fault 2 v bst iset vcc + ? figure 3. ncp3127 block diagram 10 a 0.8 v count latch & logic + ? + ? + ? ? + 0.7 v vocth dtoa counter vreg + ? table 1. pin description pin pin name description 1 pgnd the pgnd pin is the high current ground pin for the low ? side mosfet and the drivers. the pin should be soldered to a large copper area to reduce thermal resistance. 2 fb nverting input to the operational transconductance amplifier (ota). the fb pin in conjunction with the external compensation, serves to stabilize and achieve the desired output voltage with voltage mode compensation. 3 comp comp pin is used to compensate the ota which stabilizes the operation of the converter stage. place compensation components as close to the converter as possible. 4 agnd the agnd pin serves as small ? signal ground. all small ? signal ground paths should connect to the agnd pin at a single point, avoiding any high current ground returns. 5 bst supply rail for the floating top gate driver. to form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to bst pin). connect a capacitor (cbst) between this pin and the vsw pin. typical values for cbst range from 1 nf to 10 nf. ensure that cbst is placed near the ic. 6 vin the vin pin powers the internal control circuitry and is monitored by an undervoltage comparator. the vin pin is also connected to the internal power nmosfet switches. the vin pin has high di/dt edges and must be decoupled to pgnd pin close to the pin of the device. 7 iset current set pin and bottom gate mosfet driver. place a resistor to ground to set the current limit of the converter. 8 vsw the vsw pin is the connection of the drain and source of the internal n ? mosfets. the vsw pin swings from v in when the high side switch is on to small negative voltages when the low side switch is on with high dv/dt transitions.
ncp3127 http://onsemi.com 3 table 2. maximum ratings rating symbol min max unit main supply voltage input v in ? 0.3 15 v bootstrap supply voltage vs gnd v bst ? 0.3 30 v bootstrap supply voltage vs ground (spikes 50 ns) v bst spike ? 0.3 35 v bootstrap pin voltage vs v sw v bst ? v sw ? 0.3 15 v high side switch max dc current iv sw 0 3.5 v v sw pin voltage v sw ? 0.7 35 v switch pin voltage (spikes < 50 ns) v swtr ? 5.0 40 v fb pin voltage v fb ? 0.3 5.5 < v cc v comp/disable vcomp/dis ? 0.3 5.5 < v cc v low side driver pin voltage viset ? 0.3 15 < v cc v low side driver pin voltage (spikes 200 ns) viset spike ? 2 15 < v cc v rating symbol rating unit thermal resistance, junction ? to ? ambient (note 2) (note 3) r ja 110 183 c/w thermal resistance, junction ? to ? case r jc 170 c/w storage temperature range t stg ? 55 to 150 c junction operating temperature t j 0 to 125 c lead temperature soldering (10 sec): reflow (smd styles only) pb ? free rf 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. the value of ja is measured with the device mounted on 1 in 2 fr ? 4 board with 1 oz. copper, in a still air environment with t a = 25 c. the value in any given application depends on the user?s specific board design. 3. the value of ja is measured with the device mounted on minimum footprint, in a still air environment with t a = 25 c. the value in any given application depends on the user?s specific board design. 4. 60 ? 180 seconds minimum above 237 c.
ncp3127 http://onsemi.com 4 table 3. electrical characteristics ( ? 40 c < t j < 125 c; v in = 12 v, bst ? vsw = 12 v, bst = 12 v, v sw = 24 v, for min/max values unless otherwise noted.) characteristic conditions min typ max unit input voltage range v in ? gnd 4.5 13.2 v boost voltage range v bst ? gnd 4.5 26.5 v supply current quiescent supply current v fb = 1.0 v, no switching, v in = 13.2 v 1.0 ? 10.0 ma shutdown supply current ? 4.0 ? ma boost quiescent current v fb = 1.0 v, no switching, v in = 13.2 v 0.1 ? 1.0 ma under voltage lockout v in uvlo threshold v in rising edge 3.8 ? 4.3 v v in uvlo hysteresis ? ? 430 ? mv switching regulator vfb feedback voltage, control loop in regulation t j = 0 to 25 c, 4.5 v < v cc < 13.2 v ? 40 c t j 125 c, 4.5 v cc 13.2 v 0.792 0.784 0.800 0.800 0.808 0.816 mv oscillator frequency t j = 0 to 25 c, 4.5 v < v cc < 13.2 v ? 40 c t j 125 c, 4.5 v cc 13.2 v 300 290 350 350 400 410 khz ramp ? amplitude voltage 0.8 1.1 1.4 v minimum duty ratio ? 5.5 ? % maximum duty ratio 70 75 80 % pwm compensation transconductance 3.0 ? 5 ms open loop dc gain 55 70 ? db output source current output sink current v fb < 0.8 v v fb > 0.8 v 80 80 125 125 200 200 a input bias current ? 0.16 1.0 a enable enable threshold 0.3 0.4 0.5 v soft ? start delay to soft ? start 3.0 ? 15 ms ss source current v fb < 0.8 v ? 10.5 ? a switch over threshold v fb = 0.8 v ? 100 ? % of vref over ? current protection ocset current source sourced from iset pin, before ss ? 10 ? a oc switch ? over threshold ? 700 ? mv fixed oc threshold ? 375 mv pwm output stage high ? side switch on ? resistance v in = 12 v (note 5) v in = 5 v (note 5) 80 105 140 175 m low ? side switch on ? resistance v in = 12 v (note 5) v in = 5 v (note 5) 80 105 140 175 m 5. guaranteed by design.
ncp3127 http://onsemi.com 5 typical characteristics figure 4. i cc vs. temperature t j , junction temperature ( c) 120 100 60 40 20 ? 20 ? 40 ? 60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 input current (ma) 0 80 140 v cc = 12 v v cc = 5 v figure 5. input current switching vs. temperature t j , junction temperature ( c) 40 30 20 10 0 9 11 13 15 17 21 input current (ma) 19 70 60 50 v cc = 5 v v cc = 12 v 25 23 figure 6. soft ? start sourcing current vs. temperature t j , junction temperature ( c) 60 50 70 40 30 20 10 0 8 9 10 11 12 13 14 soft ? start sourcing current ( a) figure 7. reference voltage (v ref ) vs. temperature t j , junction temperature ( c) 7 0 60 50 40 30 20 10 0 792 794 796 798 800 804 806 808 v ref , reference (mv) 802 figure 8. scp threshold vs. temperature t j , junction temperature ( c) 70 60 50 40 30 20 10 0 325 335 345 355 365 375 scp threshold (mv) figure 9. minimum active duty cycle vs. temperature t j , junction temperature ( c) 40 30 20 10 0 0 1.0 2.0 3.0 4.0 6.0 duty cycle (%) 5.0 70 60 50 v cc = 5 v v cc = 12 v
ncp3127 http://onsemi.com 6 typical characteristics figure 10. duty cycle maximum vs. temperature t j , junction temperature ( c) 40 30 20 10 0 73 73.5 74 74.5 75 76 duty cycle (%) 75.5 70 60 50 v cc = 5 v v cc = 12 v load current (a) efficiency (%) figure 11. efficiency (v in = 12 v) vs. load current load current (a) figure 12. efficiency (v in = 5 v) vs. load current efficiency (%) output current (a) t a , ambient temperature figure 13. derating curve 5 v/6 v input output current (a) t a , ambient temperature figure 14. derating curve 12 v input 50 55 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.0 v 1.1 v 1.2 v 1.5 v 1.8 v 2.5 v output 0.8 v 50 55 60 65 70 75 80 85 90 95 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.0 v 1.1 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v output 0.8 v 1.2 v 0 0.5 1 1.5 2 2.5 25 35 45 55 65 75 85 1.8 v 1.2 v 3.3 v 0 0.5 1 1.5 2 2.5 25 35 45 55 65 75 85 5.0 v 3.3 v 1.2 v & 1.8 v
ncp3127 http://onsemi.com 7 general the ncp3127 is a pwm synchronous buck regulator intended to supply up to a 2 a load for dc ? dc conversion from 5 v and 12 v buses. the ncp3127 is a regulator that has integrated high ? side and low ? side nmosfets switches. the output voltage of the converter can be precisely regulated down to 800 mv 1.0% when the v fb pin is tied to v out . the switching frequency is internally set to 350 khz. a high gain operational transconductance amplifier (ota) is used for voltage mode control of the power stage. duty ratio and maximum pulse width limits in steady state dc operation, the duty ratio will stabilize at an operating point defined by the ratio of the input to the output voltage. the device can achieve a 75% duty ratio. the ncp3127 has a preset off ? time of approximately 150 ns, which ensures that the bootstrap supply is charged every switching cycle. the preset off time does not interfere with the conversion of 12 v to 0.8 v. input voltage range (v in and bst) the input voltage range for both v in and bst is 4.5 v to 13.2 v with referenced to gnd and v sw . although bst is rated at 13.2 v with respect to v sw , it can also tolerate 26.5 v with respect to gnd. external enable/disable once the input voltage has exceeded the boost and uvlo threshold at 3 v and v in threshold at 4 v, the comp pin starts to rise. the v sw node is tri ? stated until the comp voltage exceeds 0.9 v. once the 0.9 v threshold is exceeded, the part starts to switch and the part is considered enabled. when the comp pin voltage is pulled below the 400 mv threshold, it disables the pwm logic, the top mosfet is driven off, and the bottom mosfet is driven on. in the disabled mode, the ota output source current is reduced to 10 a. when disabling the ncp3127 using the comp / disable pin, an open collector or open drain drive should be used as shown in figure 16: comp 0.9 v bg tg figure 15. enable/disable driver state diagram 2n7002e comp enable disable gate signal comp enable disable base signal mmbt3904 figure 16. recommended disable circuits power sequencing power sequencing can be achieved with ncp3127 using two general purpose bipolar junction transistors or mosfets. an example of the power sequencing circuit using the external components is shown in figure 17. 1.0v vin 3.3 v figure 17. power sequencing ncp3127 fb1 vsw comp ncp3127 fb1 vsw comp input voltage shutdown behavior input voltage shutdown occurs when the ic stops switching because the input supply reaches uvlo threshold. undervoltage lockout (uvlo) is provided to ensure that unexpected behavior does not occur when vcc is too low to support the internal rails and power the converter. for the ncp3127, the uvlo is set to permit operation when converting from an input voltage of 5 v. if the uvlo is tripped, switching stops, the internal ss is discharged, and all mosfet gates are driven low. the v sw node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. external soft ? start the ncp3127 features an external soft ? start function, which reduces inrush current and overshoot of the output voltage. soft ? start is achieved by using the internal current
ncp3127 http://onsemi.com 8 source of 10 a (typ), which charges the external integrator capacitor of the ota. figure 14 is a typical soft ? start sequence. the sequence begins once v in and v bst surpass their uvlo thresholds and ocp programming is complete. the current sourced out of the comp pin continually increases the voltage until regulation is reached. once the voltage reaches 400 mv logic is enabled. when the voltage exceeds 900 mv, switching begins. current is sourced out of the comp pin, placing the regulator into open loop operation until 800 mv is sensed at the fb pin. once 800 mv is sensed at the fb pin, open loop operation ends and closed loop operation begins. in closed loop operation, the ota is capable of sourcing and sinking 120 a. figure 18. soft ? start sequence vcc comp vfb bg tg bg comparator bg comparator output vout uvlo por delay current comp delay soft ? start normal operation uvlo 0.9 v 3.85 v 4.2 v dac voltage 500 mv 50 mv trip set overcurrent threshold setting ncp3127 overcurrent threshold can be set from 50 mv to 550 mv, by adding a resistor (r set ) between iset and gnd. during a short period of time following v in rising over uvlo threshold, an internal 10 a current (i ocset ) is sourced from the iset pin, creating a voltage drop across r set . the voltage drop is compared against a stepped internal voltage ramp. once the internal stepped voltage reaches the r set voltage, the value is stored internally until power is cycled. the overall time length for the oc setting procedure is approximately 9 ms. connecting an r set resistor between iset and gnd, the programmed threshold will be: i octh i ocset *r set r ds(on) 2.0 a 10 a*21k 105 m (eq. 1) i ocset = sourced current i octh = current trip threshold r ds(on) = on resistance of the low side mosfet r set = current set resistor the r set values range from 5 k to 55 k . if r set is not connected, the device switches the ocp threshold to a fixed 375 mv value (3.57 a), an internal safety clamp on iset is triggered as soon as iset voltage reaches 700 mv, enabling the 375 mv fixed threshold and ending the ocp setting period. the current trip threshold tolerance is 25 mv. the accuracy is best at the highest set point (550 mv). the accuracy will decrease as the set point decreases. mosfet tolerances with temperature and input voltage will vary the over current set threshold operating point. a graph of the typical current limit set thresholds at 4.5 v and 12 v is shown in figure 19. output current (a) r set (k ) figure 19. r set value for output current 5.0 v 12 v 0 0.5 1 1.5 2 2.5 3 3.5 4 5 1015202530 current limit protection in case of a short circuit or overload, the low ? side (ls) fet will conduct large currents. the regulator will latch off, protecting the load and mosfets from excessive heat and damage. low ? side r ds(on) sense is implemented at the end of each ls ? fet turn ? on duration to sense the current. while the low side mosfet is on, the v sw voltage is compared to the user set internally generated ocp trip voltage. if the v sw voltage is lower than ocp trip voltage, an overcurrent condition occurs and a counter counts consecutive current trips. if the counter reaches 7, the pwm logic and both hs ? fet and ls ? fet are turned off. the regulator has to go through a power on reset (por) cycle to reset the ocp fault as shown in figure 20.
ncp3127 http://onsemi.com 9 bg + ? vocth current flow 0v vocth phase low side mosfet current bg drive figure 20. current limit trip application section design procedure when starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design. on semiconductor has a microsoft excel ? based design tool available online under the design tools section of the ncp3127 product page. the tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria. table 4. design parameters design parameter example value input voltage (v in ) 10.8 v to 13.2 v output voltage (v out ) 3.3 v input ripple voltage (v inripple ) 300 mv output ripple voltage (v outripple ) 40 mv output current rating (i out ) 2 a operating frequency (f sw ) 350 khz the buck converter produces input voltage v in pulses that are lc filtered to produce a lower dc output voltage v out . the output voltage can be changed by modifying the on time relative to the switching period t or switching frequency. the ratio of high side switch on time to the switching period is called duty ratio d. duty ratio can also be calculated using v out , v in , the low side switch voltage drop v lsd , and the high side switch voltage drop v hsd . f sw 1 t (eq. 2) d t on t and (1 d) t off t (eq. 3) d v out v lsd v in v hsd v lsd d v out v in 27.5% 3.3 v 12 v (eq. 4) d = duty cycle f sw = switching frequency t = switching period t off = high side switch off time t on = high side switch on time v hsd = high side switch voltage drop v in = input voltage v lsd = low side switch voltage drop v out = output voltage inductor selection when selecting an inductor, the designer can employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. when using ceramic output capacitors, the ripple current can be greater because the esr of the output capacitor is smaller, thus a user might select a higher ripple current. however,
ncp3127 http://onsemi.com 10 when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher esr of electrolytic capacitors. the ratio of ripple current to maximum output current is given in equation 5. ra i iout (eq. 5) i = ripple current i out = output current ra = ripple current ratio using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using equation 6. l out v out i out ra f sw (1 d) (eq. 6) 12.21 h 12 v 2.0 a
28%
350 khz (1 27.5%) d = duty ratio f sw = switching frequency i out = output current l out = output inductance ra = ripple current ratio current ripple ratio (%) figure 21. inductance vs. current ripple ratio inductance ( h) 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 10 13 16 19 22 25 28 31 34 37 40 when selecting an inductor, the designer must not exceed the current rating of the part. to keep within the bounds of the part?s maximum rating, a calculation of the rms and peak inductor current is required. i rms i out 1 ra 2 12 (eq. 7) 2.01 a 2.01 a * 1 32% 2 2 i out = output current i rms = inductor rms current ra = ripple current ratio i pk i out 1 ra 2 2.28 a 2.0 a 1 28% 2 (eq. 8) i out = output current i pk = inductor peak current ra = ripple current ratio a standard inductor should be found so the inductor will be rounded to 12 h. the inductor should also support an rms current of 2.01 a and a peak current of 2.28 a. the final selection of an output inductor has both mechanical and electrical considerations. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the lar gest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by equation 9. slewrate lout v in v out l out (eq. 9) 0.72 a s 12 v 3.3 v 12 h l out = output inductance v in = input voltage v out = maximum output voltage equation 9 implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak ? to ? peak ripple current for ncp3127 is given by the following equation: ipp v out
(1 d) l out f sw (eq. 10) 0.57 a 3.3 v
(1 27.5%) 12 h 350 khz d = duty ratio f sw = switching frequency ipp = peak ? to ? peak current of the inductor l out = output inductance v out = output voltage from equation 10 it is clear that the ripple current increases as l out decreases, emphasizing the trade ? off between dynamic response and ripple current. the power dissipation of an inductor falls into two categories: copper and core losses. the copper losses can be further categorized into dc losses and ac losses. a good first order approximation of the inductor losses can be made using the dc resistance as shown below:
ncp3127 http://onsemi.com 11 lp _dc i rms 2 dcr (eq. 11) 94 mw 2.01 a 2 23.27 m i rms = inductor rms current dcr = inductor dc resistance lp cu_dc = inductor dc power dissipation the core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. most vendors will provide the appropriate information to make accurate calculations of the power dissipation at which point the total inductor losses can be captured by the equation below: 104 mw 94 mw 0mw 10 mw (eq. 12) lp tot lp cu_dc lp cu_ac lp core lp cu_dc = inductor dc power dissipation lp cu_ac = inductor ac power dissipation lp core = inductor core power dissipation output capacitor selection the important factors to consider when selecting an output capacitor are dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. the output capacitor must be rated to handle the ripple current at full load with proper derating. the rms ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. the rms current for the output capacitor can be calculated below: co rms i out ra 12 0.164 a 2.0 a 28% 12 (eq. 13) co rms = output capacitor rms current i out = output current ra = ripple current ratio the maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (esl), and equivalent series resitance (esr). the main component of the ripple voltage is usually due to the esr of the output capacitor and the capacitance selected, which can be calculated as shown in equation 14: v esr_c i out *ra* co esr 1 8*f sw *c out (eq. 14) 28.9 mv 3 * 28% * 50 m 1 8 * 350 khz * 470 f co esr = output capacitor esr c out = output capacitance f sw = switching frequency i out = output current ra = ripple current ratio the esl of capacitors depends on the technology chosen, but tends to range from 1 nh to 20 nh, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. the calculated contributing voltage ripple from esl is shown for the switch on and switch off below: v eslon esl * ipp * f sw d (eq. 15) 7.25 mv 10 nh * 0.57 a * 350 khz 27.5% v esloff esl*ipp*f sw ( 1 d ) (eq. 16) 2.75 mv 10 nh * 0.57 a * 350 khz 1 27.5% d = duty ratio esl = capacitor inductance f sw = switching frequency ipp = peak ? to ? peak current the output capacitor is a basic component for the fast response of the power supply. for the first few microseconds of a load transient, the output capacitor supplies current to the load. once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value. during a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the esr (neglecting the effect of the esl). v out esr i tran
co esr 50 mv 1.0 a
50 m (eq. 17) co esr = output capacitor equivalent series resistance i tran = output transient current v out_esr = voltage deviation of v out due to the effects of esr a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is given by the following equation: v out dis i tran 2
l out 2
d max c out
v in v out (eq. 18) 1.96 mv 1a 2
12 h 2
75%
470 f
12 v 3.3 v c out = output capacitance d max = maximum duty ratio i tran = output transient current l out = output inductor value v in = input voltage v out = output voltage v out_dis = voltage deviation of v out due to the effects of capacitor discharge
ncp3127 http://onsemi.com 12 in a typical converter design, the esr of the output capacitor bank dominates the transient response. please note that v out ? dis and v out ? esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of the input ripple current is: iin rms i out d
(1 d) (eq. 19) 0.89 a 2.0 a * 27.5% * ( 1 27.5% ) d = duty ratio iin rms = input capacitance rms current i out = load current the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin cin esr * iin rms 2 (eq. 20) 7.98 mw 10 m * 0.89 a 2 cin esr = input capacitance equivalent series resistance iin rms = input capacitance rms current p cin = power loss in the input capacitor due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum must be used, it must be surge protected, otherwise, capacitor failure could occur. power mosfet dissipation mosfet power dissipation, package size, and the thermal environment drive power supply design. once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the high ? side mosfet will display both switching and conduction losses. the switching losses of the low side mosfet will not be calculated as it switches into nearly zero voltage and the losses are insignificant. however, the body diode in the low ? side mosfet will suffer diode losses during the non ? overlap time of the gate drivers. starting with the high ? side mosfet, the power dissipation can be approximated from: p d_hs p cond p sw_tot (eq. 21) p cond = conduction power losses p sw_tot = total switching losses p d_hs = power losses in the high side mosfet the first term in equation 21 is the conduction loss of the high ? side mosfet while it is on. p cond i rms_hs 2 r ds(on)_hs (eq. 22) i rms_hs = rms current in the high ? side mosfet r ds(on)_hs = on resistance of the high ? side mosfet p cond = conduction power losses using the ra term from equation 5, i rms becomes: i rms_hs i out d 1 ra 2 12 (eq. 23) i rms_hs = high side mosfet rms current i out = output current d = duty ratio ra = ripple current ratio the second term from equation 21 is the total switching loss and can be approximated from the following equations. p sw_tot p sw p ds p rr (eq. 24) p ds = high side mosfet drain source losses p rr = high side mosfet reverse recovery losses p sw = high side mosfet switching losses p sw_tot = high side mosfet total switching losses the first term for total switching losses from equation 24 are the losses associated with turning the high ? side mosfet on and off and the corresponding overlap in drain voltage and current. p sw p ton p toff (eq. 25) 1 2 i out v in f sw t rise t fall f sw = switching frequency i out = load current t fall = mosfet fall time t rise = mosfet rise time v in = input voltage p sw = high side mosfet switching losses p ton = turn on power losses p toff = turn off power losses
ncp3127 http://onsemi.com 13 when calculating the rise time and fall time of the high side mosfet it is important to know the charge characteristic shown in figure 22. vth figure 22. mosfet switching characteristics t rise q gd i g1 q gd v bst v th r hspu r g (eq. 26) i g1 = output current from the high ? side gate drive q gd = mosfet gate to drain gate charge r hspu = drive pull up resistance r g = mosfet gate resistance t rise = mosfet rise time v bst = boost voltage v th = mosfet gate threshold voltage t fall q gd i g2 q gd v bst v th r hspd r g (eq. 27) i g2 = output current from the low ? side gate drive q gd = mosfet gate to drain gate charge r g = mosfet gate resistance r hspd = drive pull down resistance t fall = mosfet fall time v bst = boost voltage v th = mosfet gate threshold voltage next, the mosfet output capacitance losses are caused by both the high ? side and low ? side mosfets, but are dissipated only in the high ? side mosfet. p ds 1 2 c oss v in 2 f sw (eq. 28) c oss = mosfet output capacitance at 0v f sw = switching frequency p ds = mosfet drain to source charge losses v in = input voltage finally, the loss due to the reverse recovery time of the body diode in the low ? side mosfet is shown as follows: p rr q rr v in f sw (eq. 29) f sw = switching frequency p rr = high side mosfet reverse recovery losses q rr = reverse recovery charge v in = input voltage the low ? side mosfet turns on into small negative voltages so switching losses are negligible. the low ? side mosfet?s power dissipation only consists of conduction loss due to r ds(on) and body diode loss during the non ? overlap periods. p d_ls p cond p body (eq. 30) p body = low side mosfet body diode losses p cond = low side mosfet conduction losses p d_ls = low side mosfet losses conduction loss in the low ? side mosfet is described as follows: p cond i rms_ls 2 r ds(on)_ls (eq. 31) i rms_ls = rms current in the low side r ds(on)_ls = low ? side mosfet on resistance p cond = high side mosfet conduction losses i rms_ls i out ( 1 d ) 1 ra 2 12 (eq. 32) d = duty ratio i out = load current i rms_ls = rms current in the low side ra = ripple current ratio the body diode losses can be approximated as: p body v fd i out f sw nol lh nol hl (eq. 33) f sw = switching frequency i out = load current nol hl = dead time between the high ? side mosfet turning off and the low ? side mosfet turning on, typically 50 ns nol lh = dead time between the low ? side mosfet turning off and the high ? side mosfet turning on, typically 50 ns p body = low ? side mosfet body diode losses v fd = body diode forward voltage drop control dissipation the control portion of the ic power dissipation is determined by the formula below: p c i cc
v in (eq. 34) i cc = control circuitry current draw p c = control power dissipation v in = input voltage once the ic power dissipations are determined, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case
ncp3127 http://onsemi.com 14 ambient temperature. the formula for calculating the junction temperature with the package in free air is: t j t a p d r ja (eq. 35) p d = power dissipation of the ic r ja = thermal resistance junction to ambient of the regulator package t a = ambient temperature t j = junction temperature as with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case mosfet r ds(on) ). compensation network to create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the pwm generator and the power stage. since the power stage design criteria is set by the application, the compensation network must correct the over all system response to ensure stability. the output inductor and capacitor of the power stage form a double pole at the frequency as shown in equation 36: f lc 1 2 l out
c out (eq. 36) 2.119 khz 1 2
12 h
470 f c out = output capacitor f lc = double pole inductor and capacitor frequency l out = output inductor value the esr of the output capacitor creates a ?zero? at the frequency as shown in equation 37: f esr 1 2
co esr
c out (eq. 37) 6.772 khz 1 2
0.050 m
470 f co esr = output capacitor esr c out = output capacitor f lc = output capacitor esr frequency the two equations above define the bode plot that the power stage has created or open loop response of the system. the next step is to close the loop by considering the feedback values. the closed loop crossover frequency should be greater than the f lc and less than 1/5 of the switching frequency, which would place the maximum crossover frequency at 70 khz. further, the calculated f esr frequency should meet the following: f esr f sw 5 (eq. 38) f sw = switching frequency f esr = output capacitor esr zero frequency if the criteria is not met, the compensation network may not provide stability and the output power stage must be modified. figure 23 shows a pseudo type iii transconductance error amplifier. vref r1 r2 rf cf rc cc cp gm zin zfb iea figure 23. pseudo type iii transconductance error amplifier the compensation network consists of the internal ota and the impedance networks z in (r 1 , r 2 , r f , and c f ) and external z fb (r c , c c , and c p ). the compensation network has to provide a closed loop transfer function with the highest 0 db crossing frequency to have fast response and the highest gain in dc conditions to minimize the load regulation issues. a stable control loop has a gain crossing with ? 20 db/decade slope and a phase margin greater than 45 . include worst ? case component variations when determining phase margin. to start the design, a resistor value should be chosen for r 2 from which all other components can be chosen. a good starting value is 10 k . the ncp3127 allows the output of the dc ? dc regulator to be adjusted down to 0.8 v via an external resistor divider network. the regulator will maintain 0.8 v at the feedback pin. thus, if a resistor divider circuit was placed across the feedback pin to v out , the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 v at the fb pin. fb r1 r2 v out figure 24. feedback resistor divider the relationship between the resistor divider network above and the output voltage is shown in equation 39:
ncp3127 http://onsemi.com 15 r 2 r 1 v ref v out v ref (eq. 39) r 1 = top resistor divider r 2 = bottom resistor divider v out = output voltage v ref = regulator reference voltage the most frequently used output voltages and their associated standard r 1 and r 2 values are listed in table 5. table 5. output voltage settings v o (v) r 1 (k ) r 2 (k ) 0.8 1.0 open 1.0 2.55 10 1.1 3.83 10.2 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 the compensation components for the pseudo type iii transconductance error amplifier can be calculated using the method described below. the method serves to provide a good starting place for compensation of a power supply. the values can be adjusted in real time using the compensation tool comp calc, available for download at on semiconductor?s website. the value of the feed through resistor should always be at least 2x the value of r 2 to minimize error from feed through noise. using the 2x assumption, r f will be set to 20 k and the feed through capacitor can be calculated as shown below:
ncp3127 http://onsemi.com 16 c f r 1 r 2 2
r 1 r f r 2
r f r 2
r 1
f cross (eq. 40) 239 pf 31.6 k 10 k 2
31.6 k
20 k 10 k
20 k 10 k
31.6 k
30 khz c f = feed through capacitor f cross = crossover frequency r 1 = top resistor divider r 2 = bottom resistor divider r f = feed through resistor the cross over of the overall feedback occurs at f po : 16.86 khz 31.6 k 20 k 2 2
239 pf 2 31.6 k 20 k
20 k 10 k
20 k
20 k 31.6 k
1.1 v 2.119 khz
12 v (eq. 41) f po r 1 r f 2 2
c f 2 r 1 r f
r 2 r 1
r f
r f r 1
v ramp flc
v in c f = feed through capacitor f lc = frequency of the output inductor and capacitor f po = pole frequency r 1 = top of resistor divider r 2 = bottom of resistor divider r f = feed through resistor v in = input voltage v ramp = peak ? to ? peak voltage of the ramp the cross over combined compensation network can be used to calculate the transconductance output compensation network as follows: c c 1 f po 4
r 2 r 2
r 1
gm (eq. 42) 57.5 nf 1 16.86 khz
10 k 10 k 31.6 k
4ms c c = compensation capacitor f po = pole frequency gm = transconductance of amplifier r 1 = top of resistor divider r 2 = bottom of resistor divider
ncp3127 http://onsemi.com 17 r c 1 2
f lc
c c
2 2 f cross
co esr
c out (eq. 43) 2.9 k 1 2
2.119 khz
57.5 nf
2 2 30 khz
0.05 m
470 f c c = compensation capacitance co esr = output capacitor esr c out = output capacitance f cross = crossover frequency f lc = output inductor and capacitor frequency r c = compensation resistor c p c out
co esr r c
2
(eq. 44) 1.288 nf 470 f
0.05 m 2.9 k
2* co esr = output capacitor esr c out = output capacitor c p = compensation pole capacitor r c = compensation resistor
ncp3127 http://onsemi.com 18 assuming an output capacitance of 470 f in parallel with 22 f with a crossover frequency of 35 khz, the compensation values for common output voltages can be calculated as shown in table 6: table 6. compensation values v in (v) v out (v) l out ( f) cf (nf) cc (nf) rc (k ) cp (nf) 12 0.8 4.7 ni 150 0.536 3.3 12 1.0 4.7 390 150 0.649 2.7 12 1.1 4.7 390 150 0.732 2.7 12 1.2 6.8 330 120 1.1 1.5 12 1.5 6.8 330 120 1.27 1.5 12 1.8 8.2 270 120 1.82 1.2 12 2.5 10.0 220 120 2.87 1.0 12 3.3 12.0 1000 100 3.16 0.680 12 5.0 15.0 1000 100 4.02 0.560 5 0.8 4.7 ni 150 1.27 1.5 5 1.0 4.7 390 150 1.62 1.2 5 1.1 5.6 390 150 1.91 1.0 5 1.2 5.6 330 150 2.15 0.82 5 1.5 6.8 330 150 2.74 0.68 5 1.8 8.2 270 150 4.42 0.56 5 2.5 10.0 220 150 5.36 0.39 calculating soft ? start time to calculate the soft ? start delay and soft ? start time, the following equations can be used. t ssdelay c p c c
0.9 v i ss (eq. 45) 7.64 ms 1.28 nf 83.6 nf
0.9 v 10 a c p = compensation pole capacitor c c = compensation capacitor i ss = soft ? start current the time the output voltage takes to increase from 0 v to a regulated output voltage is t ss as shown in equation 46: t ss c p c c
d
v ramp i ss (eq. 46) 2.57 ms 1.28 nf 83.6 nf
27.5%
1.1 v 10 a c p = compensation pole capacitor c c = compensation capacitor d = duty ratio i ss = soft ? start current t ss = soft ? start interval v ramp = peak ? to ? peak voltage of the ramp v 900 mv vcomp vout figure 25. soft ? start ramp the delay from the char ging of the compensation network to the bottom of the ramp is considered t ssdelay . the total delay time is the addition of the current set delay and t ssdelay , which in this case is 6 ms and 7.64 ms respectively, for a total of 13.64 ms. calculating input inrush current the input inrush current has two distinct stages: input charging and output charging. the input charging of a buck stage is usually not controlled, and is limited only by the input rc network, and the output impedance of the upstream power stage. if the upstream power stage is a perfect voltage source, then the input charge inrush current can be depicted as shown in figure 26 and calculated as: ipk figure 26. input charge inrush current i icinrush_pk 1 v in cin esr (eq. 47) 120 a 12 0.1
ncp3127 http://onsemi.com 19 i icinrush_rms 1 v in cin esr
1 1 e t delay_total cin esr
c in (eq. 48)
0.316
5
0.1
330 f 13.64 ms
0.316
5
cin esr
c in t delay_total 102 ma 12 v 0.1
1 1 e 13.64 ms 0.1
330 f c in = output capacitor cin esr = output capacitor esr t delay_ total = total delay interval v in = input voltage once the t delay_total has expired, the buck converter starts to switch and a second inrush current can be calculated: i ocinrush_rms c out c load
v out t ss d 3 i cl
d (eq. 49) c out = total converter output capacitance c load = total load capacitance d = duty ratio of the load i cl = applied load at the output i ocinrush_rms = rms inrush current during start ? up t ss = soft ? start interval v out = output voltage from the above equation, it is clear that the inrush current is dependant on the type of load that is connected to the output. two types of load are considered in figure 27: a resistive load and a stepped current load. ncp3127 load or inrush current figure 27. load connected to the output stage if the load is resistive in nature, the output current will increase with soft ? start linearly which can be quantified in equation 50. i clr _rms 1 3
v out r out (eq. 50) 191 ma 1 3
3.3 v 10 i cr_pk v out r out 330 ma 3.3 v 10 r out = output resistance v out = output voltage i clr_rms = rms resistor current i cr_pk = peak resistor current
ncp3127 http://onsemi.com 20 tss output current output voltage 3.3 v figure 28. resistive load current alternatively, if the output has an under voltage lockout, turns on at a defined voltage level, and draws a consistent current, then the rms connected load current is: i cli v out v out_to v out
i out (eq. 51) 492 ma 3.3 v 2.5 v 3.3 v
1a i out = output current v out = output voltage v out_to = output voltage load turn on tss t 1.0 v 3.3 v output current output voltage figure 29. voltage enable load current if the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using i 2 t methodology. layout considerations as in any high frequency switching regulator, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. the interconnecting impedances should be minimized by using wide short printed circuit traces. the critical components should be located as close together as possible using ground plane construction or single point grounding. for optimal performance, the ncp3127 should have a layout similar to the one shown in figure 30. an important note is that the input voltage to the ncp3127 should have local decoupling to pgnd. the recommended decoupling for input voltage is a 1 f general purpose ceramic capacitor and a 0.01 f cog ceramic capacitor placed in parallel. to p bottom agnd ????? ????? ????? ????? ????? ? ? ?? ?? ?? figure 30. recommended layout the typical applications are shown in figures 31 and no tag for output electrolytic and ceramic bulk capacitors, respectively.
ncp3127 http://onsemi.com 21 figure 31. standard application 12 v to 2.5 v 2 a vin vout lout 10uh c1 10uf 16v d1 mmsd4148t1g c4 22uf 6.3v r1 21.5k r2 10k c10 1uf 25v r3 20r cbst 10nf 50v cf 1.2nf 10v vin gnd_in vout gnd c11 0.01uf 25v rset 21k vsw fb bst cc 68n 50v cp 820pf 50v rc 2.94k c9 1nf 25v r9 100r comp 1 2 3 4 8 7 6 5 u1 ncp3127 rf 20k c5 ni chf 820pf 50v c3 470uf 16v gnd pgnd fb comp agnd vsw iset vin bst c2 ni 16v r4 20r jx c8 ni rcr ni c6 ni 6.3v c7 470uf 16v vin vout lout 8.2uh c1 10uf 16v d1 mmsd4148t1g c4 22uf 6.3v r1 12.7k r2 10.2k c10 1uf 25v r3 20r cbst 10nf 50v cf 1nf 10v vin gnd_in vout gnd c11 0.01uf 25v rset 21k vsw fb bst cc 330n 50v cp ni 50v rc 392 c9 1nf 25v r9 100r comp 1 2 3 4 8 7 6 5 u1 ncp3127 rf 3.01k c5 47uf 6.3v chf 820pf 50v gnd pgnd fb comp agnd vsw iset vin bst c2 10uf 16v r4 20r jx c8 ni rcr 150m figure 32. ceramic capacitor application 12 v to 1.8 v 2 a
ncp3127 http://onsemi.com 22 figure 33. application bottom layout (top) figure 34. application top layout (top)
ncp3127 http://onsemi.com 23 table 7. ncp3127 application bill of materials item reference qty description value tolerance footprint manufacturer manufacturer part name 1 c11 1 smt ceramic capacitor 0.01 f 5% 0603 tdk c1608c0g1e103j 2 cf 1 smt ceramic capacitor 1.2 nf 5% 0603 avx 0603zc122jat4a 3 c10 1 smt ceramic capacitor 1 f 10% 0603 avx 06033d105kat2a 4 cc 1 smt ceramic capacitor 68n 5% 0603 avx 06035c683jat2a 5 chf cp 2 smt ceramic capacitor 820 pf 5% 0603 avx 06035a821jat2a 6 c8 1 smt ceramic capacitor ni 0603 7 cbst 1 smt ceramic capacitor 10 nf 20% 0805 avx 08055c681mat2a 8 c9 1 smt ceramic capacitor 1 nf 20% 0805 avx 08053c102mat2a 9 c1 1 smt ceramic capacitor 10 f 10% 1210 avx 1210yd106kat2a 10 c4 1 smt ceramic capacitor 22 f 10% 1210 avx 12106z226mat2a 11 c2 1 smt ceramic capacitor ni 1210 12 c5 1 smt ceramic capacitor ni 1210 13 c3 c7 2 surface mount e ? cap 470 f 20% (8.30 x 8.30) mm panasonic eee ? fp1c471ap 14 c6 1 surface mount e ? cap ni 20% (10.3 x 10.3) mm united chemicon emza160ada471mha0g 15 d1 1 switching diode 1 a, 100 v sod ? 123 on semiconductor mmsd4148t1g 16 lout 1 inductor, sm 10 h 20% (12.3 x 12.3) mm coilcraft mss1278 ? 103ml 17 u1 1 synchronous pwm switching converter 285 khz, 0.8 v na soic ? 8 on semiconductor ncp3127 18 rcr 1 smt resistor ni 1206 19 r2 1 resistor 10k 1.0% 0603 vishay / dale crcw060310k0fkea 20 rc 1 resistor 2.94k 1.0% 0603 vishay / dale crcw06032k94fkea 21 r3 ? 4 2 resistor 20r 1.0% 0603 vishay / dale crcw060320r0fkea 22 rf 1 resistor 20k 1.0% 0603 vishay / dale crcw060320k0fkea 23 r1 1 smt resistor 21.5k 1.0% 0603 vishay / dale crcw060321k5fkea 24 rset 1 resistor 21k 1.0% 0603 vishay / dale crcw060321k0fkea ordering information device package shipping ? NCP3127ADR2G soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp3127 http://onsemi.com 24 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp3127/d microsoft excel is a registered trademark of microsoft corporation. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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